Embedded Signal Processing
Low Power Reconfigurable Receiver Architectures for Migrating Software Defined Radio Technology from Base Stations to Handsets
Most of the research in software defined radio (SDR) has been focused on SDR base stations, which do not have as tight constraints on area and power as handsets. However, as the technology matures, SDR designs are targeted for migration from base stations to handsets where their true potential can be realized. The additional area and power constraints imposed by handsets with limited resources pose a major design challenge. Addressing this challenge, my research focused on low power reconfigurable receiver architectures for migrating SDR technology from base stations to handsets. New low-complexity architectures for SDR channelizer, which is the most computationally intensive block in the digital frontend, have been proposed. Several techniques such as Common subexpression elimination method, Constant shift method, Programmable shift method, Reconfigurable frequency response masking technique, Coefficient-decimation method, Fractional delay-based method, etc. were proposed for integrating low complexity and reconfigurability into a single architecture for implementing the channelizer in the digital front-end of SDR receiver.
Low Complexity Dynamically Reconfigurable Signal Processing for Cognitive Radios
Cognitive Radio (CR) is a promising future wireless communication technology to provide opportunistic spectrum access of the vacant frequency bands to a group of users called secondary users for whom the band has not been licensed. The key functionalities of a CR are to sense the spectral environment over a wide frequency band (spectrum sensing) and exploit the spectrum occupancy information to opportunistically provide wireless links that best meet the user communications requirements (channel adaptation). My research focused on the research issues relating to the design and realization of low complexity dynamically (run-time) reconfigurable signal processing for spectrum sensing and channel adaptation in Cognitive Radio (CR) terminals.
Design techniques for low complexity high-speed spectrum sensing techniques that enabled extraction of the multiple bandwidth channels present in the wideband input signal by using variable-resolution spectrum sensing were proposed. New low power hardware efficient spectrum sensing methods were proposed. Further, design of truly reconfigurable hardware-efficient channelizer architectures to meet the requirements of a low power, dynamically reconfigurability for channel adaptation in CR was done. Methods to identify and extract the multiple bandwidth channels were proposed using techniques such as Multistage frequency response masking based filter bank channelizers, Filter banks based on Cascaded Interpolation and Masking filters and Coefficient-Decimation Filter Banks. We also designed power efficient techniques for cooperative spectrum sensing by investigating a low power computationally efficient cooperative spectrum sensing using location information. A high resolution, low complexity cooperative spectrum sensingalgorithm was also proposed. The proposed spectrum sensing and channel adaptation techniques were implemented on FPGA to evaluate area, power consumption and speed comparisons with conventional methods.