Due to epidemiological transitions in India, there is a trend of increasing ageing population and therefore, it is essential to develop innovative programs aimed at the maintenance of their independence and well-being. The remarkable finding of brain plasticity has made revolutionary changes in the concept of brain to re-organize its structure, even in the elderly, through neurofeedback training. Neurofeedback allows self-regulation of brain signal based on the real time visual/audio feedback, and can be utilized to slow down the deterioration of cognitive capabilities, motor skills and emotional well-being of the elderly, mild or earlier stages of dementia, stroke and Parkinson’s disease (PD) patients, by fine tuning their respective neural correlates. In this project, we develop a noninvasive Electroencephalography (EEG) based Brain-Machine Interface (BMI) system for neuro-enhancement of patients who are at the mild or earlier stages of neurological disorders, particularly stroke, dementia and PD. The proposed neuro-enhancement and neurorehabilitation technique comprises of design, development and experiments with neurofeedback games, virtual reality environments and a humanoid robot, controlled by user’s EEG signals associated with attention, memory, motor imagery (movement imagination) and visually evoked potentials. The system developed in this project will be validated in National Institute of Mental Health and Neurosciences (NIMHANS) Bangalore, India, and its impact will be evaluated statistically using standard assessment tools and patients’ personal experiences.

This project aims to develop a brainwave based drowsiness detection system using commercial-grade portable wireless EEG.

The aim of this project is to design and develop a low-cost Pulse Oximeter for ICUs. Clinical cohort study with the prototypes developed was conducted on 200 Covid-19 patients in hospitals.

The motor system of human brain responsible for the movement skill development and the neural modulations within the motor system resulting in a wide range of fine, gross and complex movement tasks are widely investigated research areas in neuroscience. Brain Computer Interface (BCI) is a neuroengineering technology which is being developed as a potential alternative and augmentative communication and control tool, primarily targeted for disabled people. It employs a novel mode of interaction between brain and external world, accomplished solely by brain activity, bypassing brain's normal communication and control pathway of nerves and muscles. Specifically, BCI systems dedicated to motor research and applications, explore and decode the sensorimotor activations of brain to provide motor control to external effectors. This project investigates the applicability of an Electroencephalography (EEG) based BCI system to continuously decode kinematics of an imagined hand movement reaching task. The proposed system will use EEG as the BCI data acquisition modality owing to its non-invasiveness, portability and low cost. The system will be developed as a closed-loop neurofeedback system which allows the BCI user to receive on-line information of his brain activity and to voluntarily regulate specific parameters of brain patterns through training. The hand movement task used in this study is an imagined reaching task towards a visually-guided target location. The parameters of hand movement such as speed and position encoded in distinct brain patterns will be identified, extracted and decoded using the proposed BCI system. The project also proposes a BCI interface, which is a novel and engaging experiment platform that provides visual cues and feedback for the user. The BCI output will be provided as motor control to an on-screen object or a virtual robotic arm, which serves as the neurofeedback. The project will also develop synchronous and asynchronous modes of the same interface and evaluate the system performance. Further, the project will also investigate the components of sensorimotor processing such as motor, visuomotor, visuospatial skills involved in the imagined movement task.

The significant contribution of this research will be developing a robust BCI system that can decode imagined movement kinematics from noninvasive EEG signal, to provide higher order motor control command to an interfaced effector and thereby create a thought-controlled device. The novel experiment interface to study the sensorimotor processing responsible for imagined movement parameters and neurofeedback learning to enhance the user performance will also be developed. The project will conduct a comprehensive study on motor, visuomotor and visuospatial skills of the user involved in imagined movement kinematics task and will identify the underlying neural correlates. Finally, the neurofeedback (BCI output) will be used as a motor control command to the interfaced virtual object. This will establish a thought-controlled virtual robotic arm with ability to move towards multiple target locations at different speeds and has potential benefits towards BCI applications such as neuro prosthetics and robotics.

Increased traffic demand especially the ASIAN region is expected to increase. Airports such as Singapore Changi, Beijing International Airports and China, Heathrow Airport, United Kingdom have examined various initiatives to increase their air traffic management capacities ranging from building additional runways, optimizing flight scheduling and routing between cities and redesign of airspace. This projected increase in traffic capacity brings with it new challenges to systems modelling and management of ATM operations. Besides technology challenges, accurate capturing of the workload and performance when subjected to high traffic volume, manning and coordination tasks amongst air traffic controllers (ATC) in real time would also need to be studied. It must be said that the ATC manning procedures and operational tasks differ pending on the path segments of the flight during en-route, terminal manoeuvre area or ground movements.

This project seeks to investigate into the relationships between psycho and physiological factors such as cognitive profile (brain activity mapping), attention level (visual eye tracking movements), stress level (blood pressure and pulse rate), emotion (facial expressions) and fatigue (locomotion actions) of ATC operators. These human factors are examined as they have bearing on the level of safety, work performance, efficiency and health of operators functioning an individual or team undertaking at a designated set of air traffic conditions.

The aim of this project is to identify innovative methods to manage interference that will increase in future high capacity multi-beam satellite transmissions, as technology advances and the market expands. This will enable greater growth opportunities for operators, especially using multi-beam and multi-satellite systems.

Satellite communications is the only alternative for maritime and aeronautical communications and extensively used in sparsely populated regions. Satellite-based networks are reliable compared to the terrestrial networks because of their isolation from the natural calamities like cyclones, flooding and earthquakes, etc., and hence they are essential for the disaster management. The key resource required to meet the ever increasing demand for the data communication through the satellite networks is the spectrum, which is, unfortunately, scarce and costly. Aggressive reuse of the spectrum is advocated to improve the spectrum utilization efficiency, and it leads to co-channel interference-limited satellite systems. The goal of the present work is to improve the spectrum utilization efficiency of the satellite network through proper interference management for the emerging satellite communication architectures. In particular, the present project studies the interference management techniques for cooperative, heterogeneous and cognitive satellite networks.

In cooperative satellite networks, two satellites each serving own set of multiple users are assumed to be co-located on the same frequency. The downlink (DL) and uplink (UL) of such a network can be modeled as multiple-input-multiple-output interference broadcast channels (MIMO IFBC) and MIMO interfering multiple access channels (MIMO IFMAC), respectively. The two satellites can cooperate through the inter satellite link (ISL) or through the backhaul link between the gateways. For the integrated terrestrial and satellite network (also called as heterogeneous network), the satellite and the terrestrial networks are assumed to operating on the same frequency. Satellite is connected through gateway to the terrestrial core network. This system can be modeled as the MIMO interference channel (MIMO IC) with transmitter cooperation or MIMO IC with receiver cooperation or MIMO IC with both the transmitter and receiver cooperation. Interference management through relay is another option. With relay, the above channel models turn into MIMO IFBC with relay, MIMO IFMAC with relay and MIMO IC with relay (MIMO ICR).

In the cognitive satellite network, satellite and terrestrial networks are assumed to be operating on the same frequency and are co-located. The cognitive satellite network can be modeled as MIMO X channel. Based on the levels of interference, it can be degraded to a Z-channel or a parallel channel with no interference. In the present work, optimal transmission schemes for the above channel models will be designed. In particular, the proposed research will investigate algorithms for the interference management using overlay cognitive radio technique.

The proposed approach for each of the above channel models is to use the cooperative precoding along with innovative channel encoding and decoding schemes. The proposed algorithms will be implemented using WARPLab based testbed.

This project seeks to investigate into the relationships between psycho and physiological factors such as cognitive profile (brain activity mapping), attention level (visual eye tracking movements), stress level (blood pressure and pulse rate), emotion (facial expressions) and fatigue (locomotion actions) of ATC operators. These human factors are examined as they have bearing on the level of safety, work performance, efficiency and health of operators functioning an individual or team undertaking at a designated set of air traffic conditions.

Recognition of persons based on their unique physiological or behavioral characteristics, named as biometric identification or authentication, has received great research attention from scientific community during the last decade. Biometric features extracted from finger prints, iris, face, brain waves etc., have shown superior performance over traditional modalities of personal identification numbers, access cards etc., in terms of security, stability and robustness. Among the existing biometric traits, brain wave based biometric has been emerging as a strong candidate on account of its extreme uniqueness and the impossibility to steal or mimic. The non-invasive Electroencephalogram (EEG), one of the most appropriate techniques to acquire brain activity, due to its simplicity, portability and reasonable-price, has been studied by the scientific community to develop biometric systems. EEG patterns, captured from persons at relaxed rest state with closed/open eyes or active states while performing certain mental activities, have been reported as robust carriers of unique personality traits.

During the initial period of the project, we have done an extensive literature review on EEG based biometric systems. Basically a biometric system operates in three modes: (i) enrollment mode, (ii) authentication/verification mode and (iii) identification mode. Enrollment is to register the identity of a new person in the database (the storage of biometric templates) using his/her typical EEG features. This consists of 3 major stages, namely data acquisition, pre-processing and feature extraction. Data acquisition deals with the collection of raw EEG data from subjects. Preprocessing step performs data cleaning and noise removal from the collected EEG. Feature extraction module extracts salient and informative features to generate a subject-specific distinct EEG templates. Authentication is to confirm or deny an identity claim by a particular individual whereas identification is to identify an individual from a pool of persons. During identification and authentication, the data acquisition, pre-processing and feature exaction modules function in similar manner, but identification requires one to many matching (comparison with all templates in the database) whereas authentication requires only one to one matching (comparison with the claimed identity's template only) for recognition of subjects. Depending upon the matching score computed, the recognition system accepts the claimed person as a client or rejects as an imposter. Performance of an identification system is assessed by correct recognition rate (CRR) and an authentication system is assessed by error rates named as False Acceptance Rates (FAR), False Rejection Rate (FRR) and Equal Error Rate (ERR). In order to achieve good performance, CRR should be high as possible and error rates should be low as possible.

Motivated by the fact that EEG patterns during eyes closed/open rest state are potential characteristics for developing biometric systems, we have developed a number of offline and online biometric systems using the related EEG patterns. As peak frequency of alpha band (8-12 Hz) and delta band (0.5- 4 Hz) during rest state have been reported as a neurophysiological markers of personality traits, we have proposed a biometric identification system combining subject-specific alpha peak frequency, peak power and delta band power values to form representative feature vectors as well as discriminative templates. We have also developed systems using sample entropy features and gamma band power spectral density (PSD) features of EEG during rest state, for biometric authentication and identification. A number of online systems have also been developed using rest state and using EEG responses to visual and auditory stimulus, for recognition of subjects. The proposed offline systems gives highest accuracy of about 98% among 109 subjects, and online system offers an accuracy of 88.33% among 6 subjects. In future, we will evaluate the proposed methods in bigger population, in real time environments and optimize the system performance with robust signal processing and machine learning techniques.

The goal of this project was to develop a cognitive radio (CR) based A/G communication network that provides dynamic spectrum access to airplanes to overcome the spectrum scarcity problem, which is inevitable to tackle the communication requirements of the ever increasing air-traffic.

A novel energy difference based spectrum sensing technique was developed wherein spectrum holes, i.e., unused frequency bands in the aeronautical spectrum allotted to LDACS1 can be detected. A variable digital filter (VDF) based spectrum sensing approach was proposed, wherein a VDF is used to obtain any bandwidth for sensing the occupancy of the desired frequency band.

State-of-the-art of the aeronautical communication systems (ACS) and their spectral requirements were surveyed. The need for the cognitive radio in ACS is highlighted and various cognitive modes of operation suitable for the ACS were proposed. Half-duplex decode-and-forward (DF), dynamic DF (DDF) relay-assisted interference cancellation techniques to mitigate the interference in cognitive radio based ACS were developed. Single-user and multi-user codes based transmission schemes from the perspective of interference mitigation were also investigated. A relaying technique was devised for achieving higher data rates and lower power consumption in air-ground communication, wherein intermediate aircrafts are used to relay (receive and forward) the communication signals from other aircrafts to the ground stations. An ingenious algorithm for efficient and interference-limited Time Frequency Unit (TFU) allocation to aircrafts within adjacent service volumes (SV) was developed. A novel approach for mitigating the pulsed interference from DME towards LDACS1 systems was proposed.

Low complexity channel filter and filter banks were designed for onboard and ground-station based LDACS1 receivers respectively. These are pioneering works that propose low complexity channelization using filters and filter banks for LDACS1 receivers. A radio architecture based on the latest generation FPGAs that offers advanced capabilities like partial reconfiguration, for enabling cognitive radio based air-ground communication was developed. A novel computationally efficient synchronization method for L-DACS1 systems that offers robust performance was developed.

In this project, we developed a computer game that can be controlled using attention level of the player, which helps children suffering from attention-deficit hyperactivity disorder (ADHD) to boost their concentration abilities. The system also provides neurofeedback through on-screen visual display of the player's current attention level, which allows self-regulation of brain signals based on the visual feedback. In the game we developed, attention level of the player, quantified using sample entropy values of brain waves acquired using Electroencephalogram (EEG) signals, is the core neurofeedback element. Its value is continuously displayed during the game which helps the player to fine tune his mental strategy and related brain waves to optimize attention level. The game is designed such that the player has to memorize a set of numbers in a matrix, and to correctly re-fill the matrix using his attention based EEG. The progress and rewards in the game solely depend on the magnitude and consistency of player's attention scores estimated from EEG. During the study, eight healthy subjects played the proposed neurofeedback game for a period of one week. Experimental results showed that the game performance and attention scores improve over days for all players. Cognitive tests have also been conducted before and after the neurofeedback training, and the obtained results showed the applicability of the proposed game in enhancing cognitive skills too.

People with diseases like Autism, Alzheimer's disease or Parkinson's disease have impairment to understand other people's emotions. Children with autism spectrum disorder have great hurdles in understanding and responding to emotional and mental states (happiness, sadness, anger, disgust etc.) in others' facial expressions. The inability to understand other people's emotions will hinder their interpersonal communication. This project developed a real-time portable emotion detection system that will aid such children to interact with the external world easily by enabling them to understand facial emotions during their face to face communication. An ultra-light camera fixed to the head gear of the Autistic subject captures facial images of the person with whom the autistic subject interacts. The camera sends the images to a Field Programmable Gate Array (FPGA) for processing (pre-processing, feature extraction and classification). The facial emotion recognition algorithm running on FPGA is optimized taking into account of hardware resource constraints while achieving acceptable classification accuracy. The objective of the project was to study the research issues relating to the design of a real time emotion recognition algorithm and to implement the same in hardware.

While numerous techniques have been proposed to detect human emotions based on facial expressions, there have been only a few researches on the potential of implementing the emotion recognition system on a compact, portable hardware platform. Our key challenge was to implement the emotion recognition algorithm in hardware so that area and power efficiency along with portability can be achieved. The initial work was based on Jacobi iteration to calculate the Eigen values and vectors for emotion recognition. Jacobi iteration allows simultaneous evaluation of all the Eigen values and vectors. We have proposed an improved implementation of Jacobi iteration for an efficient emotion recognizer. We carried out the implementation using Xilinx ISE 13.2 (Verilog). The target system is Virtex 7 XC7VX330T FFG1761-3 FPGA. The design is implemented with wordlengths of 8 bits and 12 bits. The key area and power consuming operation in the emotion recognition is the feature extraction. In our method, we have made the principal component analysis (PCA) hardware efficient by calculating only the diagonal and upper triangular matrix by exploiting the symmetry property of the covariance matrix. We have compared the PCA of the proposed emotion recognizer with the conventional PCA where the full covariance matrix is used to calculate the Eigen vectors and values. We were able to achieve 72.3 % detection accuracy for a wordlength of 8 bit and 72.9% detection accuracy for a wordlength of 12 bit.

We found that parallel implementation enables faster operation but it has high area and power consumption. We proposed an algorithm to analyze and find out through simulations the minimum image size and Eigen range for which the accuracy remains within the required range. Hence we use power iteration and deflation method to produce the Eigen values and vectors within that optimized Eigen range rather than calculating the full Eigen range as in Jacobi or QR method. After obtaining the optimum image size and Eigen range, we use power-deflation iteration. We were able to achieve power reduction of 49.5% at the cost of a delay overhead of 23.2% when compared to Jacobi method. The delay is due to the fact that the proposed method calculates the Eigen values and vectors serially. We classified the emotions with reference to neutral face. Using the proposed method, we achieved a classification accuracy of 82.3% for a wordlength of 8 bits.

From the above works we understood that there should be a clear comparison between the most efficient serial and parallel implementation for better understanding of selecting the best method for developing an emotion recognizer for autistic children. We have done an implementation comparison between parallel and serial calculation of Eigen values and vectors to exploit the same to aid an autistic person. We have used Jacobi implementation to be the best hardware efficient parallel method whereas Rayleigh quotient method to be the best serial method for implementation. A choice of best emotion detector implementation will purely depend on our choice on speed, resource utilization and power. The proposed Rayleigh quotient method can arrive at the same accuracy with 62.5% lesser area and 57.7% lesser power with delay increment of 52% when compared to the parallel Jacobi method. Hence the optimal choice of low power emotion detection method will be Rayleigh method and the fastest emotion detection method to be Jacobi method.

Cognitive Radio (CR) is a promising future wireless communication technology to provide opportunistic spectrum access of the vacant frequency bands to a group of users called secondary users for whom the band has not been licensed. The key functionalities of a CR are to sense the spectral environment over a wide frequency band (spectrum sensing) and exploit the spectrum occupancy information to opportunistically provide wireless links that best meet the user communications requirements (channel adaptation). The objective of this project is to address the research issues relating to the design and realization of low complexity dynamically (run-time) reconfigurable signal processing for spectrum sensing and channel adaptation in Cognitive Radio (CR) terminals.

The main objective of the project is to design and realization of low complexity dynamically (run-time) reconfigurable signal processing for spectrum sensing and channel adaptation in CR terminals. We address techniques that enable low complexity realization of flexible digital signal processing operations for spectrum sensing and channel adaptation. Our specific aim is to propose computing techniques that enable low complexity realization of flexible digital signal processing operations for spectrum sensing and channel adaptation.

Fast and accurate spectrum sensing is essential in CR to identify and extract the multiple bandwidth channels present in the wideband input signal. We have proposed three methods for multi-resolution spectrum sensing. The first method is a modified Discrete Fourier Transform Filter Bank (DFTFB), which can be reconfigured to change the sensing resolution over different time intervals with reduced hardware complexity. In the proposed DFTFB, the prototype filter is implemented using the coefficient decimation approach proposed by us. The second multi-resolution scheme is a modified Fast Filter Bank (FFB) which is inherently low complex and works on the principle of frequency response masking scheme. The output response of the FFB depends on the interpolated modal or prototype filter response. If the interpolation factors of the modal filter can be reconfigured with the corresponding masking filter stages of FFB, a filter bank with channels of different bandwidths can be realized. The third method is a progressive decimation filter bank (PDFB), which provides variable sensing resolutions and can adapt to different detection bandwidths. Only software reconfiguration is needed when the sensing requirement (resolution and\or detection bandwidth) changes. This is achieved by the relatively lower dependency on the number of subbands of its structure compared to other approaches. The proposed sensing architecture does not limit the optimization methods used in constructing the prototype filter. Furthermore, the proposed PDFB based spectrum sensor can also eliminate the use of channelizer in the following stage, as the same spectrum sensor filter bank can be used to extract occupied channels.

We have proposed a low complexity reconfigurable FB channelizer based on coefficient decimation, interpolation and frequency masking techniques. The proposed FB architecture is capable of extracting channels of distinct (non-uniform) bandwidths from the wideband input signal. In many practical scenarios, it is desirable to change the cut-off frequency of a digital filter in real time with minimal overhead on complexity. Such a filter with variable cut-off frequency is called as variable digital filter (VDF). We have proposed new method for the design of FIR filter that provides variable frequency responses. The proposed idea is to replace each unit delay operator in a fixed-coefficient FIR filter with the second order FIR fractional delay (FD) structure and the cut-off frequency of the filter is changed by changing the FD value.

We have also investigated the role of parallelism as a power reduction strategy in nanoscale CMOS implementations. We have proposed a class of programmable time-shared FIR filters based on fast filter algorithms, that can trade area for increased timing slack, more efficiently than traditional folded direct form filters. We have also identified the range for filter lengths for which the proposed class of filters are more area efficient.

All the designs of the reconfigurable filters need to be of low complexity for reduced power and area. We have also proposed, an FIR filter implementation using Residue Number System (RNS), that can be reconfigured to satisfy the filter frequency response specification of a new communication standard when the receiver switches its operation from its current standard to a new standard, in a multi-standard wireless communications scenario. Existing RNS based FIR filter implementations focus on achieving different dynamic range, and there is hardly any work addressing reconfiguration for a different frequency response specification. The encoder hardware proposed is by exploiting the commutative multiplication property between quantized input signal and filter coefficients. Also, the synthesis results of a 350-tap Digital Advanced Mobile Phone Systems (D-AMPS) channel filter as well as comparison of proposed product encoder with several other methods were obtained.

The performance of a cognitive radio system depends on how well it can maximize the usage of a free frequency band without causing any interference to the primary user. Conventional energy detectors (ED) are based on a fixed threshold. This may not be optimum in low Signal to Noise Ratio (SNR) conditions where the performance of fixed threshold based detector can vary from the targeted performance metrics substantially. We have proposed a method to change the threshold based on the number of samples, to optimize the detection parameters, namely probability of detection and probability of false alarm. We introduced a control parameter to vary the set threshold and thereby obtain a response more suited to the operational requirements than that obtained by a fixed threshold based ED.

We have proposed a two-stage detection mechanism which gives an improved performance over conventional single stage detectors yet optimizes the usage of the second-stage, thereby reducing the sensing time as compared to conventional two-stage spectrum sensing algorithms. The proposed two-stage detector employs ED in the first-stage and a boosted pilot subcarrier for cyclic frequency detection in the second-stage. The use of cyclic frequency detection aims to mitigate the problems due to noise uncertainty faced by ED at low SNRs. We pre-compute the lower bound of the SNR at which the ED still works satisfactorily and show that by estimating the SNR of the channel the cognitive radio is in, we can switch off the second-stage of a two-stage detector when the channel SNR is higher than the lower bound of the SNR level of the ED. We show that this does not cause any loss of performance. The hardware implementation of the ED and pilot assisted detection (PACD) techniques shows that the dynamic power requirement of the PACD is five times that of the ED. Hence switching off the PACD stage leads to enormous savings in power consumption. Thus the proposed two-stage detector not only leads to savings in the mean detection time of the CR, it also lowers the dynamic power of the CR device by 84% which is a limiting factor for any battery operated device.

A novel method for a power efficient cooperative spectrum sensing scheme is proposed which uses location information and employs a censoring method to reduce the average number of sensing bits sent to the common receiver. The reduction in the number of sensing bits using proposed method in turn reduces the total transmission power of the secondary users in the cognitive network thus improving its battery life.

We have proposed a cooperative spectrum sensing scheme which provides accurate detection at low complexity, by assigning different sensing tasks to the CRs. If the number of cooperative CRs is N, our method which employs progressive decimation filter banks, offer an effective sensing resolution of N times higher than that of the conventional method. This is achieved using an inherently low complex progressive decimation filter bank at each CR, which provides variable sensing resolutions by software reconfiguration.

A new approach to distinguish signal from noise using fuzzy logic was proposed. Unlike conventional energy detection method where a single threshold is used for decision making, the output decision of fuzzy logic is obtained by taking into account several possibilities, which provides a more robust conclusion on the decision. The proposed method can also detect edges of radio channels (frequency bands) in the wideband input signal when the channel bandwidths are unknown. The computational complexity of the proposed method is much less than wavelet based spectrum edge detection and is easier to implement. Investigations were done in the field of reconfigurable constant multiplier (RCM) and the synthesis results on some practical RCMs and randomly generated sets of constants show that the proposed algorithm produces solutions which are up to 25% more area-time efficient than the latest and best reported solutions known in the literature for 12-bit constant sets. A follow-up research was also done on potential power reduction by logic depth optimization of fixed coefficient FIR filters modeled as Multiple Constant Multiplication (MCM) problem. Our study concluded that CSE algorithm cannot find all beneficial shared patterns from any signed digit representation of the coefficient set as the nonzero digits in the addends are hidden, converted to different SD and switched in position. Based on the insight, we proposed a minimal LD GD algorithm that requires no lookup table.

A cyber-physical thermal management scheme is explored to automatically control the temperature of 3DIC chip below certain threshold. The cooling method is liquid cooling through interlayer micro-fluid channels. Those channels are clustered and flowrate of each cluster is controlled by one micro-pump which will be adjusted based on real-time work load demands. This will be very useful for the heat removal procedure for the 3D integrated CR system which is heterogeneous in nature since it comprises of both analog and digital components.

The new mobile broadband technology is rapidly growing towards a fifth generation (5G), as there is an increasing demand for high data rate devices. The advent of new wireless communication services renders the electromagnetic spectrum congested. This congestion, coupled with rigid allocation of spectrum to the new wireless systems, leads to inefficient spectrum utilization and causes an apparent spectrum scarcity. Cognitive radio (CR) is envisaged as a solution to tackle the problem of this apparent spectrum scarcity. It is a conscious radio, which opportunistically uses the spectrum of a licensed user known as primary user (PU) while causing minimal interference to them. It utilizes software-defined radio (SDR) to adapt its transmission properties to match the required standards. In order to determine the spectral vacancies, the CR has to locate the PU signals accurately known as spectrum sensing. In addition, after detecting the signal, the CR must be able to classify the detected signal into a known user type. This project focused on various methods for accurate wideband detection and modulation classification for a stand-alone CR scenario in the physical layer domain. These methods operate with partial knowledge about the PUs signal and/or the noise environment. They can also extract certain features of the signal spectrum such as edge frequencies and modulation scheme in a robust manner. In general, the research problem of signal detection and classification is addressed using these three methods- filter bank based detectors, higher order statistics and fractional lower order statistics.

In the first work, filter bank based detection method that helps in determining the location of the vacant bands, by locating the PU signal and its edge frequencies was presented. In order to increase the granularity and efficiency of detection, the method involves a new multi-stage discrete Fourier transform filter bank based energy detector. An algorithm was proposed that determines the edge frequencies of the PU channels using the properties of filter bank and the information from the energy detector. Simulation and computational analysis show that the proposed method gives a good balance between accuracy and complexity. The design example and simulations showed that the gate count resource utilization of our detection scheme is 22.9% lesser than the wavelets based detection method at the cost of a slight degradation of 0.5% in detection accuracy. This method provides a good foundation to understand the underlying problem of spectrum sensing and its challenges.

The algorithms in the first work are based on second-order statistics where the noise has a degrading effect on the signal. The sensing becomes even more challenging in the presence of strong interferers, noisy environment or under fading conditions. To mitigate this, the second work proposed a detection and classification algorithm based on higher-order statistics and fractional lower order statistics. Spectrum sensing is performed using the proposed test statistic for detection that incorporates modified cumulants derived using fractional lower order statistics (FLOS). The performance of the proposed method was compared with the conventional method based on higher order statistics (HOS) for various noise conditions. It has been shown that the proposed method performs well in both Gaussian and non-Gaussian conditions as compared to the conventional method. An experimental data acquisition setup was employed to obtain real time signals from the wideband spectrum to analyze the noise characteristics. The main advantage of the proposed method is that the same statistic used for detection is also used for classification.

After locating the vacant bands, the CR is required to change its transceiver parameters to use the vacant band opportunistically, which is achieved using SDR technology. In the third work, a CR scheme including a policy engine, two-stage spectrum sensing unit and an SDR is elucidated. The focus is on the working of a real-time policy engine with a two-stage spectrum sensing unit that aids policy driven cognitive radio. A new two-stage filter bank based energy detector and cumulants method has been proposed for accurate spectrum sensing. The filter bank used for channelization is used for spectrum sensing as well, resulting in complexity reduction.

Furthermore, the validation of some existing and proposed algorithms using real world signals captured using a USRP2 radio and GNURadio framework was also conducted. The main contribution of the work was on improved sensing and classification methods for cognitive radios and military radios. By deploying SDR, an overall framework for spectrum sensing based policy-driven CR has been demonstrated.

This project addressed following tasks:
- Initiated the triggering of the ADCs for coherent sampling and time-tagging of the digitalized samples. The ADC shall be sampling at 25.6MHz.
- Digitized the wideband input signal at sampling frequency of 25.6 MHz using the onboard ADC.
- Implemented reconfigurable filter banks on the onboard FPGA to extract individual channels of 25 kHz from the digitized wideband input signal.
- Implemented a user defined threshold detector for each of the extracted channels using the onboard FPGA.

This project was to design and implement a low power wireless communication channelizer and signal detector for spectral analysis and filtering. The receiver must extract all the channels of wideband input signal and is constrained to work with very little priori knowledge of the number of channels, bandwidths of different channels and channel locations (centre frequencies). The receiver should be able to adapt to time-varying input signal in real-time and therefore it must be dynamically reconfigurable. And all the receiver functionalities must be implemented with low power consumption and low area (compact design).

Conventional channelizers employ uniform Discrete Fourier Transform filter banks (DFTFBs). These kind of channelizers can only extract fixed bandwidth channels and result in high complexity when used for analyzing dynamically changing channels with various bandwidths. Besides this conventional approach, we analyzed different available channelization methods and identified the merits and demerits of each method. Since the military radio receiver needs a spectrum sensor to obtain the knowledge of the input, we also studied the spectrum sensing techniques. Then we proposed three reconfigurable architectures to sense and channelize the signal with low power consumption.

A new spectrum sensor based on Multi-stage Coefficient Decimation filter bank (MS-CDFB) has been proposed. The proposed spectrum sensor performs spectrum sensing of wideband input signal with no priori spectrum knowledge. It is constructed from a fixed coefficient modal filter and can adapt to different splitting requirements. It has low complexity and high reconfigurability compared to conventional DFTFB spectrum sensor while offering similar sensing accuracy as that of the DFTFB based spectrum sensor.

A conventional DFTFB-based spectrum sensor can only provide fixed sensing resolution due to its uniform bandwidth characteristic. A spectrum sensing technique based on progressive decimation filter bank (PDFB) has been proposed in this report. The filter bank is constructed from a single finite impulse response (FIR) filter with low design effort. It can have variable sensing resolutions and adapt to different detection bandwidths. Only software reconfiguration is needed when the sensing requirement (resolution and\or detection bandwidth) changes. Design examples show that the detection performance is reasonably good and similar to the conventional DFTFB based spectrum sensor. Furthermore, the proposed PDFB based spectrum sensor can also eliminate the use of channelizer in the following stage, as the same spectrum sensor filter bank can be used to extract occupied channels. This system has been implemented on Xilinx Virtex 2v3000ff1152-4 FPGA and it shows that the proposed spectrum sensor consumes the least area without heavy penalty on time and power when comparing to DFTFB and Cosine-Modulated filter bank (CMFB).

A sensing scheme which provides higher sensing resolution by assigning radio receivers different sensing tasks was proposed. The higher resolution is achieved at the cost (power, complexity) of a low resolution filter bank at each receiver. Progressive decimation filter banks (PDFBs) are used in these receivers as the PDFB has very low complexity while providing variable sensing resolutions by software reconfiguration. Using the proposed algorithm, the center node can derive the spectrum information of narrower frequency segments from the outputs of the sensing nodes. This gives a higher effective sensing resolution, while the filter banks used are of relatively low sensing resolution. Therefore, the design saves resource consuming by the cooperation of these low cost nodes. The functionality was verified by the design examples and it shows the proposed system has a convincing performance that is close to the performance of a conventional DFTFB based spectrum sensor.

We proposed a new low complexity reconfigurable filter bank architecture based on frequency response masking technique for multi-standard cognitive radios. In conventional multi-standard filter bank, a separate filter bank is needed for each standard, and reconfigurability is achieved by switching among distinct filter banks. This is not an efficient approach due to its increased hardware complexity and poor resource utilization. Our proposed reconfigurable filter bank reuses the same hardware for multiple communication standards, while ensuring low complexity.

A graphical approach for the optimization of multi-standard software defined radio (SDR) systems was proposed. Computational complexity for multi-standards multi-channels channelizers has been analyzed and results of the optimization procedure as applied to channelizer branch of flexible systems showed that frequency response masking technique is most suitable as compared to others.

A reconfigurable architecture for arbitrary sample rate conversion (SRC) in SDRs has been proposed. Firstly we derived an efficient factorization of the overall conversion factor, so that the integral and fractional parts of the conversion load can be performed by low power building blocks. Secondly we proposed a method to determine the optimum order in which these factors should be implemented and finally we also proposed low power reconfigurable hardware architectures to implement the SRC.

The goal of this project was to evolve a framework for designing flexible, power efficient and area efficient multistandard channelization accelerators in the digital front-end of next generation software defined radio (SDR) handsets. These accelerators should be capable of selecting a channel of arbitrary bandwidth and also perform a sample rate conversion (SRC) operation by arbitrary integral or rational factors. They should also provide sufficient attenuation of interferers, blockers and out of band quantization noise, so that that the co-channel interference due to aliasing, and the carrier to noise ratio is below the permissible limits for all modes of operation. A limited power budget and a limited silicon area are the overarching design constraints in a mobile handset. Emerging communication paradigms like cognitive radios impose a very high flexibility requirement on the underlying. The time taken to reconfigure the physical hardware for operation in a different vacant band reduces the time available for useful communication, which in turn reduces the achievable throughput. Hence the reconfiguration latency of the hardware accelerators is also an important constraint in reconfigurable radios. The work conducted in this project seeks to reduce the area, power and reconfiguration latency penalty incurred when variable channelization parameters need to be supported by the channelization accelerator.

The contributions of this project can be clubbed into two broad categories. Firstly, we have investigated strategies for reducing flexibility requirement of the a multistandard channelization accelerator by identifying opportunities for reusing fixed hardwired hardware blocks that can be reused across multiple standards with low reconfiguration overheads. Secondly, we have investigated strategies for minimizing the area and power penalty of the portions of the channelization accelerator that need to be fully reprogrammable. The specific strategies are elaborated below.

The principal channelization tasks of filtering and decimation by a large sample rate conversion factor can be efficiently performed by a multistage decimation filter. The filter stages in the above multistage filter represent a naturally coarse level of granularity for investigating hardware reuse. The ability to hardwire and reuse these stages across multiple standards is limited by their dependency on standard specific parameters. The fixed factorization method proposed in this thesis factorizes any arbitrary integral or rational SRC factor into a regular form. This allows the band edge and stopband attenuation of all the filter stages prior to the last stage to be modified in a manner which allows them to be hardwired and reused across multiple standards with very low reconfiguration overheads. Experimental synthesis results have been used to demonstrate the area and power advantage of the proposed accelerator over traditional designs.

The last stage filter in the fixed factorization method needs to be fully reprogrammable to support standard band edges, roll-off factors and stop band attenuations. Reprogrammability can be supported by time-multiplexing the filtering operations onto a set of generic MAC units. Such a filter can be reprogrammed by simply updating the coefficient memory. However time-shared filters with generic MAC units incur a significant dynamic power consumption penalty when compared to a spatial style implementation of a constant coefficient filter. Hence the last stage filter dominates the overall power consumption of multistandard decimation filters designed using the fixed factorization method. In this work, we proposed a class of time-shared filter derived from fast filter algorithm (FFA) structures. These filters exploit the property of algorithmic strength reduction offered by FFA structures to reduce the number of expensive MAC operations at the cost of increased add operations. The proposed class of time-shared filters are more area/power efficient than traditional direct-form based time-shared structures, when the levels of parallelism are increased.

The objective of this research project was to develop low power reconfigurable receiver architectures for migrating Software Defined Radio (SDR) technology from base stations to handsets. We addressed the issues related to the additional area and power constraints imposed by the resource-constrained handsets, which is a major design challenge in migrating SDR from base stations to handsets.

Concepts from the generalized sampling theory for non-bandlimited signals has been combined with the theory for sampling signals with finite rate of innovation to study the minimum sampling rate requirements for signals in shift invariant spaces. We have established the formal relationship between the rate of innovation of the signal and the sampling kernel for perfect reconstruction. We showed through some examples that our proposed method to calculate the rate of innovation is accurate and the way to identify a suitable sampling kernel to achieve minimum sampling is valid.

Our further work focused on proposing new low complexity architectures for SDR channelizer, which is the most computationally intensive block in the digital front-end. We have proposed a new Common Subexpression Elimination (CSE) technique based on binary representation of filter coefficients which resulted in better reduction of channel filter complexity than existing methods proposed in literature. The proposed CSE method produces filters with fewer adders without increasing the delay. New methodologies have been developed for the design of reduced complexity high-speed digital filters. The methods are applicable to other relevant digital signal processing problems that can be transformed to a MCM model. A new Hamming Weight Pyramid (HWP) analytical structure has been proposed to analyze the properties of canonical signed digit (CSD) numbers. These properties have been exploited to develop elegant algorithm for the direct conversion of decimal number to CSD form, and overcome the limit imposed on n-Dimensional Reduced Adder Graph (RAG-n) algorithm.

In addition to low complexity, reconfigurability is another key requirement in SDR channelizers. We have proposed two new reconfigurable and low complexity FIR filter architectures for SDRs. Our first method known as constant shifts method (CSM) focuses on direct implementation of FIR filters without using programmable shifters (PS). Our second method known as programmable shifts method (PSM) employing programmable shifters offers significant power reduction. In contrast to conventional shift and add units used in previously proposed reconfigurable filter architectures, we use the binary common subexpressions-based shift and add unit in our proposed CSM and PSM architectures. To the best of our knowledge, this is the first attempt for integrating low complexity and reconfigurability into a single architecture for implementing higher order FIR filters.

We have also investigated other low complexity FIR filter design approaches such as frequency response masking (FRM) to further minimize the filter complexity and power consumption. We have realized reconfigurable multimode filter bank channelizers using the FRM approach. The proposed filter banks could extract channels of non-uniform bandwidth and extremely narrow passbands compared to other filter banks in literature. Further, we have extended the single-stage FRM approach to realize a multi-mode filter bank architecture based on multi-stage FRM approach. The proposed architecture offers multiple levels of reconfigurability depending on the number of stages of FRM. Design examples show that the proposed architecture offers complexity reduction of 38.08% over the single-stage FRM approach and 97.2% over the conventional Per-Channel (PC) approach and DFT filter banks (DFTFBs).

A new approach to implement computationally efficient reconfigurable FIR filter has been proposed. If the coefficients of an FIR filter are decimated by M, i.e., if every Mth coefficient of the filter is kept unchanged and remaining coefficients are changed to zeros, a multi-band frequency response will be obtained. The resulting frequency responses will have centre frequencies at 2Πk/M, where k is an integer ranging from 0 to M-1. If these multi-band frequency responses are selectively masked using inherently low complex wide transition-band masking filters, different low-pass, high-pass, bandpass, and bandstop filters can be obtained. If every Mth coefficient is grouped together removing the zero coefficients in between, a decimated frequency response in comparison to the original frequency response is obtained. We have also designed a reconfigurable filter bank using the above approach. A low complexity reconfigurable filter architecture based on multi-band filtering and frequency masking techniques for dynamic channel adaptation in cognitive radio terminal has been proposed. The proposed multi-standard architecture is capable of adapting to channels having different bandwidths corresponding to the channel spacing of time varying channels. Design examples showed that proposed architecture offers 12.2 % power reduction and 26.5 % average gate count reduction over conventional Per-Channel based architecture.

Efficient implementation of the sample rate converter is extremely important to reduce the power consumption of software defined radios. This becomes even more important when sigma delta converters are used for the analog to digital conversion, due to the very high oversampling rates involved. In a multistandard radio, the sample rate converter should also be capable of handling variable conversion ratios. We proposed a scheme to efficiently factorize any large rational or integer factor and map these factors onto the same underlying hardware blocks. We also suggested efficient reconfigurable architectures to implement these conversion factors.

Some efficient architectures of reconfigurable multi-moduli modulo multipliers and scalable finite field multipliers are also proposed to tackle the changing security requirements of public key cryptographic processing in multi-mode SDR.

We have synthesized the FRM filter bank-based SDR channelizer on 0.18μm CMOS technology and compared with PC approach and DFTFB. Synthesis results showed that the proposed channelizer offers area reduction of 85% over PC approach and 67.3% over DFTFB, power reduction of 48.5% over PC approach and 25.5% over DFTFB and improvement in speed of 56.7% over PC approach and 42.4% over DFTFB. We have implemented the proposed channelizer on Xilinx Virtex 2v3000ff1152-4 FPGA and tested the implementation using real-time inputs.